The present invention relates to an integrated circuit, in particular to an integrated circuit including a successive approximation type analog/digital converter circuit that compares an analog input signal with a plurality of comparison reference voltages and converts the analog input signal into a digital signal on the basis of the comparison result.
Generally, a processing circuit is formed of a digital circuit, and thus an analog signal is converted into a digital signal and then used for processing. For example, an analog signal is inputted into a processor such as a microcomputer from a sensor that detects operation environment, such as a temperature sensor or a speed sensor. The processor converts the analog signal into a digital signal and performs processing in accordance with the operation environment detected by the sensor on the basis of the digital signal.
The conversion from the analog signal to the digital signal is performed by an analog/digital converter circuit (A/D converter circuit). One of the A/D converter circuits is a successive approximation register A/D converter circuit (SAR ADC: Successive Approximation Register Analog Digital Converter).
The successive approximation register A/D converter samples an inputted analog signal and compares the sampled input signal with a comparison reference signal generated by a built-in D/A converter (digital/analog converter) through the use of a comparator. The successive approximation register A/D converter generates the next comparison reference signal in accordance with the comparison result through the use of the built-in D/A converter. The successive approximation register A/D converter converts an analog signal into a digital signal by repetition of the above operation.
A normal successive approximation register A/D converter performs analog/digital conversion through the use of a binary search algorithm. An A/D conversion of N-bit resolution is performed by N steps (N comparisons). The comparator compares an analog input signal Vin with a comparison signal (comparison reference voltage). In the first step, the comparison reference voltage Vref (1) is 2^(N−1). In the comparison result, when the analog input signal Vin is larger than the first comparison reference voltage Vref (1), the comparator outputs “1” and the comparison reference voltage Vref (2) in the second step is represented by the following formula:Vref(2)=2^(N−1)+2^(N−2)
In contrast, when the analog input signal Vin is lower than the first comparison reference voltage Vref (1), the comparator outputs “−1” (0) and the comparison reference voltage Vref (2) is represented by the following formula:Vref(2)=2^(N−1)−2^(N−2)
That is, in the binary search algorithm, the next comparison reference voltage is obtained by adding or subtracting ½ of the comparison reference voltage of the previous cycle in accordance with the comparison result.
As shown in Japanese Patent Laid-Open No. 2010-124405 (Patent Document 1), an operation sequence of the successive approximation register A/D converter is divided into (1) a sampling period in which an input analog signal is sampled by a sample hold circuit and (2) a comparison period in which an N-bit digital signal is obtained by a comparator and the like. For example, 10-bit A/D conversion is performed by assigning 11 states to the sampling period and 10 states to the comparison period.